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1 ds05-10163-2e fujitsu semiconductor data sheet memory cos 4 m 1 bit fast page mode dynamic ram MB814100D-60/-70 cmos 4,194,304 1 bit fast mode dynamic ram n description the fujitsu mb814100d is a fully decoded cmos dynamic ram (dram) that contains 4,194,304 memory cells in 4m 1 con?uration. the mb814100d features a ?ast page mode of operation whereby high-speed random access of up to 2,048-bits of data within the same row can be selected. the mb814100d dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and wide bandwidth are basic requirements of the design. since the standby current of the mb814100d is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb814100d is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon process. this process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb814100d are not critical and all inputs are ttl compatible. n product line & features parameter MB814100D-60 mb814100d-70 ras access time 60 ns max. 70 ns max. cas access time 15 ns max. 20 ns max. address access time 30 ns max. 35 ns max. randam cycle time 110 ns min. 125 ns min. fast page mode cycle time 40 ns min. 45 ns min. low power dissipation operating current 605 mw max. 550 mw max. standby current 11 mw max. (ttl level) / 5.5 mw max. (cmos level) 4,194,304 words 1 bit organization silicon gate, cmos, 3d-stacked capacitor cell all input and output are ttl compatible 1024 refresh cycles every 16.4 ms ras only, cas -before-ras , or hidden refresh fast page mode, read-modify-write capability on chip substrate bias generator for high performance this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 MB814100D-60/mb814100d-70 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ? to +7 v voltage of v cc supply relative to v ss v cc ? to +7 v power dissipation p d 1.0 w short circuit output current i out 50 ma storage temperature t stg ?5 to +125 c (lcc-26p-m04) plastic soj package package and ordering information ?26-pin plastic (300 mil) soj, order as mb814100d-xxpjn
3 MB814100D-60/mb814100d-70 n capacitance (t a =25 c, f = 1mhz) parameter symbol typ. max. unit input capacitance, a 0 to a 10 , d in cin 1 ? pf input capacitance, ras , cas , we cin 2 ? pf output capacitance, d out c out ? pf fig. 1 ?mb814100d dynamic ram ?block diagram clock gen #1 write clock gen mode control clock gen #2 column decoder sense ampl & i/o gate 4,194,304 bit storage cell data in buffer data out buffer address buffer pre- decoder refresh address counter row decoder substrate bias gen & a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 ras cas we d in d out v cc v ss
4 MB814100D-60/mb814100d-70 n pin assignments and descriptions n recommended operating conditions * : reference voltage : v ss = 0 v note: recommended operating conditions are the recommended values for guarantee of lsis normal logic operations. under this conditions, the limits value of electrical characteristic (ad/dc)is guaranteed. parameter notes symbol min. typ. max. unit ambient operating temp supply voltage* v cc 4.5 5.0 5.5 v 0 5 c to + 70 c v ss 000 input high voltage, all inputs* v ih 2.4 6.5 v input low voltage, all inputs* v il ?.0 0.8 v v ss v cc we ras a 0 to a 10 cas d in d out 26-pin soj: 1 2 3 4 5 14 15 16 9 10 11 12 13 26 25 24 23 22 18 17 designator function write enable. row address strobe. address inputs. +5 volt power supply. column address strobe. circuit ground. v cc d in we ras nc. a 10 a 0 a 1 a 2 a 3 a 8 a 7 a 6 a 5 a 4 cas nc. a 9 v ss d out data input data output (top view) 1 1 1
5 MB814100D-60/mb814100d-70 n functional operation address inputs twenty two input bits are required to decode any one of 4,194,304 cell addresses in the memory matrix. since only eleven address bits are available, the column and row inputs are separately strobed by cas and ras as shown in figure 5. first, eleven row address bits are input on pins a 0 -through-a 10 and latched with the row address strobe (ras ) then, eleven column address bits are input and latched with the column address strobe (cas ). both row and column addresses must be stable on or before the falling edge of cas and ras , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min.)+ t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of two basic ways--an early write cycle and a read-modify-write cycle. the falling edge of we or cas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data is strobed by cas and the setup/hold times are referenced to cas because we goes low before cas . in a delayed write or a read-modify-write cycle, we goes low after cas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max.) is satis?d. t cac : from the falling edge of cas when t rcd is greater than t rcd (max.). t aa : from column address input when t rad is greater than t rad (max.). the data remains valid until cas returns to a high logic level. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. fast page mode of operation the fast page mode of operation provides faster memory access and lower power dissipation. the fast page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each fast page of memory, any of 2,048-bits can be accessed and, when multiple mb 814100ds are used, cas is decoded to select the desired memory fast page. fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted.
6 MB814100D-60/mb814100d-70 n dc characteristics (recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol condition values unit min. typ. max. output high voltage v oh i oh = ?.0 ma 2.4 v output low voltage v ol i ol = 4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in 5.5 v; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i o(l) 0v v out 5.5v; data out disabled ?0 10 operating current (average power supply current) MB814100D-60 i cc1 ras & cas cycling; t rc = min. ma mb814100d-70 standby current (power supply current) ttl level i cc2 ras = cas = v ih ma cmos level ras = cas 3 v cc ?0.2 v refresh current #1 (average power supply current) MB814100D-60 i cc3 cas = v ih , ras cycling; t rc = min. ma mb814100d-70 fast page mode current MB814100D-60 i cc4 ras = v il, cas cycling; t pc = min. ma mb814100d-70 refresh current #2 (average power supply current) MB814100D-60 i cc5 ras cycling; cas -before-ras ; t rc = min. ma mb814100d-70 1 1 2 110 100 2.0 1.0 2 110 100 2 55 50 2 110 100
7 MB814100D-60/mb814100d-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol MB814100D-60 mb814100d-70 unit min. max. min. max. 1 time between refresh t ref 16.4 16.4 ms 2 random read/write cycle time t rc 110 125 ns 3 read-modify-writecycle time t rwc 130 150 ns 4 access time from ras t rac ?0?0ns 5 access time from cas t cac ?5?0ns 6 column address access time t aa ?0?5ns 7 output hold time t oh 0?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time t off ?5?5ns 10 transition time t t 250250ns 11 ras precharge time t rp 40?5ns 12 ras pulse width t ras 60 100000 70 100000 ns 13 ras hold time t rsh 15?0ns 14 cas to ras precharge time t crp 5?ns 15 ras to cas delay time t rcd 20 45 20 50 ns 16 cas pulse width t cas 15?0ns 17 cas hold time t csh 60?0ns 18 cas precharge time (normal) t cpn 10?0ns 19 row address set up time t asr 0?ns 20 row address hold time t rah 10?0ns 21 column address set up time t asc 0?ns 22 column address hold time t cah 15?5ns 23 ras to column address delay tim t rad 15 30 15 35 ns 24 column address to ras lead time t ral 30?5ns 25 column address to cas lead time t cal 30?5ns 26 read command set up time t rcs 0?ns 27 read command and hold time referenced to ras t rrh 0?ns 28 read command and hold time referenced to cas t rch 0?ns 29 write command set up time t wcs 0?ns 30 write command hold time t wch 10?0ns 6, 9 7, 9 8, 9 10 11, 12 17 13 14 14 15
8 MB814100D-60/mb814100d-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol MB814100D-60 mb814100d-70 unit min. max. min. max. 31 we pulse width t wp 10?0ns 32 write command to ras lead time t rwl 15?0ns 33 write command to cas lead time t cwl 20?0ns 34 din set up time t ds 0?ns 35 din hold time t dh 15/18 15/18 ns 36 ras to we delay time t rwd 60?0ns 37 cas to we delay time t cwd 15?0ns 38 column address to we lead time t awd 30?5ns 39 ras precharge time to cas active time (refresh cycles) t rpc 10?0ns 40 cas set up time for cas -before- ras refresh t csr 0?ns 41 cas hold time for cas -before- ras refresh t chr 10?0ns 42 we set up time from ras * 18 t wsr 10?0ns 43 we hold time from ras * 18 t whr 10?0ns 44 fast page mode ras pulse width t rasp 200000 200000 ns 45 fast page mode read/write cycle time t pc 40?5ns 46 fast page mode read-modify-write cycle time t prwc 65?0ns 47 access time from cas precharge t cpa ?5?0ns 48 fast page mode cas precharge time t cp 10?0ns 49 fast page mode ras hold time cas precharge t rhcp 35?0ns 50 fast page mode cas precharge time we delay time t cpwd 35?0ns 19 15 15 15 18 18 9, 16
9 MB814100D-60/mb814100d-70 notes: 1. referenced to v ss . 2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > ?.5 v. i cc1 , i cc3 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih. i cc4 is speci?d at one time of address change during one page cycle. 3. an initial pause (ras =cas =v ih ) of 200 m s is required after power-up followed by ras only refresh cycle or cas before ras refresh cycle (we = ?? before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of ras only refresh cycle are required. 4. ac characteristics assume t t = 5 ns. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min.) and v il (max.). 6. assumes that t rcd t rcd (max.) and t rad t rad (max.). if t rcd > t rcd (max.) or t rad > t rad (max.), t rac will be increased by the amount that t rcd or t rcd exceeds the maximum recommended value shown in this table. refer to fig. 2 and 3. 7. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac t t , access time is t cac . 8. if t rad 3 t rad (max.) and t asc t aa ?t cac t t , access time is t aa . 9. measured with a load equivalent to two ttl loads and 100 pf. 10. t off is speci?d that output buffer change to high impedance state. 11. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 12. t rcd (min.) = t rah (min.)+ 2 t t + t asc (min.). 13. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access time is controlled exclusively by t cac or t aa . 14. either t rrh or t rch must be satis?d for a read cycle. 15. t wcs , t rwd, t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is a early-write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if t wrd 3 t wrd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read-modify-write cycle and data out pin will contain data read from the selected cell. if we is falled when neither of above sets of conditions is satis?d, the cycle is a delayed- write cycle and the writing to the selected cell is executed when t rwl , t cwl, t cal and t ral are satis?d, but the condition of the data out pin is indeterminated. 16. t cpa is access time from the selection of a new column address (that is caused by changing cas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max.). 17. assumes that cas -before-ras refresh. 18. assumes that test mode function. 19. if t rcd t rcd (max.), t dh = 18 ns. otherwise, t dh = 15 ns
10 MB814100D-60/mb814100d-70 60 ns version 70 ns version 140 120 100 80 60 20 40 60 80 100 120 100 90 80 70 60 10 30 40 50 60 40 50 80 70 60 50 40 10 20 30 40 50 60 30 60 ns version 70 ns version 20 70 ns version 60 ns version fig. 2 ?t rac vs. t rcd fig. 4 ?t cpa vs. t cp fig. 3 ?t rac vs. t rad t rac (ns) t rac (ns) t cpa (ns) t rcd (ns) t rad (ns) t cp (ns)
11 MB814100D-60/mb814100d-70 n functional truth table x; ? or ? *; it is impossible in fast page mode operation mode clock input address input data refresh note ras cas we row column input oupput standby h h x high-z read cycle l l h valid valid valid yes* t rcs 3 t rcs (min.) write cycle (early write) l l l valid valid valid high-z yes* t wcs 3 t wcs (min.) read-modify-write cycle llh ? l valid valid x ? valid valid yes* t cwd 3 t cwd (min.) ras -only refresh cycle l h x valid high-z yes cas -before-ras refresh cycle l l h high-z yes t csr 3 t csr (min.) hidden refresh cycle h ? l l h valid yes previous data is kept. test mode set cycle (cbr) l l l high-z yes t csr 3 t csr (min.) t wsr 3 t wsr (min.) test mode set cycle (hidden) h ? l l l valid yes t csr 3 t csr (min.) t wsr 3 t wsr (min.)
12 MB814100D-60/mb814100d-70 t cah ? or ? row add valid data high-z fig. 5 ?read cycle column add description to implement a read operation, a valid address is latched in by the ras and cas address strobes and with we set to a high level, the output is valid once the memory access time has elapsed. the access time is determined by ras (t rac ), cas (t cac ), or column addresses (t aa ), if t rcd (ras to cas delay time) is greater than the specification, the access time is t aa under the following conditions: if t rcd > t rcd (max.), access time = t cac . if t rad > t rad (max.), access time = t aa . d out a 0 to a 10 cas v ih v il v ih v il we v ih v il v ih v il ras v ih v il t rc t ras t crp t rcd t csh t rp t rsh t cas t rad t ral t rah t asc t asr t cal t oh t rch t rcs t aa t cac t rac t off t on t rrh
13 MB814100D-60/mb814100d-70 ? or ? row valid data i n add column add high-z description a write cycle is similar to a read cycle except we is set to a low state. a write cycle can be implemented in either of two ways - early write or read-modify-write. the input data is latched with the later falling edge of cas or we and written into memory. during all write cycles, timing parameters t rwl , t cwl, t cal and t ral must be satisfied. ras d in v ih v il a 0 to a 10 cas v ih v il v ih v il we v ih v il v ih v il d out v oh v ol fig. 6 ?early write cycle t rc t ras t crp t rad t rcd t csh t cas t rsh t asc t rah t asr t cal t ral t cah t rp t wch t wcs t ds t dh
14 MB814100D-60/mb814100d-70 d in v ih v il description the read-modify-write cycle is executed by changing we from high to low after the read operation is implemented. ras v ih v il a 0 to a 10 cas v ih v il v ih v il we v ih v il d out v oh v ol ? or ? col row add add high-z valid data i n valid data out fig. 7 ?read?odify?rite?ycle t rwc t ras t csh t rp t rsh t cas t rcd t rad t rah t asc t awd t wp t cwd t cwl t cah t rwl t ral t rcs t ds t dh t oh t off t rwd t cac t rac t aa t on t crp t asr
15 MB814100D-60/mb814100d-70 t rac t cas description the fast page mode read cycle is executed after normal cycle with holding ras ?? applying column address and cas , and keep- ing we ??. once an address is selected normally using the ras and cas , other addresses in the same row can be selected by only changing the column address and applying the cas . any of the 2048 bits belonging to each row can be accessed. ras v ih v il a 0 to a 10 cas v ih v il v ih v il we v ih v il d out v oh v ol fig. 8 ?fast page mode read cycle ? or ? valid data col row add add col add col add high-z t rasp t rhcp t rp t rsh t pc t csh t cp t cas t crp t rcd t asr t rad t rah t asc t cah t asc t cah t cah t rcs t rch t rcs t on t rch t rrh t rch t aa t off t cac t cac t aa t oh t oh t on t off t cpa t ral t cal t asc
16 MB814100D-60/mb814100d-70 description the fast page mode write cycle is executed by the same manner as fast page mode read cycle except for the state of we . the data on din pin is latched with the falling edge of cas and written into the memory. the input data is latched with the later falling edge of cas or we and written into memory. any of the 2048 bits belonging to each row can be accessed. in this mode, refresh operation is not supported . the condition of refresh time must be satisfied and ras timing must be determined well. ras d in v ih v il a 0 to a 10 cas v ih v il v ih v il we v ih v il v ih v il d out v oh v ol fig. 9 ?fast page mode write cycle (early write cycle) ? or ?l high-z valid data valid data valid data col row add add col add col add t rasp t rhcp t rsh t rp t cas t cas t cp t pc t csh t crp t rcd t cas t rah t asr t asc t cah t asc t cah t cal t asc t cah t ral t wcs t wch t cwl t wch t wcs t wcl t wcs t wch t cwl t wp t ds t dh t ds t dh t dh t ds t wp t wp t rwl t rad
17 MB814100D-60/mb814100d-70 description during fast page mode, the read-modify-write cycle can be executed by changing we high to low after the data appears at d pin as well as normal cycle. ras d in v ih v il a 0 to a 10 cas v ih v il v ih v il we v ih v il v ih v il d out v oh v ol fig. 10 ?fast page mode read-modify?rite cycle ? or ? valid data col row add add col add col add valid data out valid valid data out valid data i n valid data i n valid data i n data out t rasp t rpwc t rsh t rp t pc t csh t crp t rcd t cas t cas t rad t rah t asr t asc t cah t asc t cah t cal t cac t asc t rwl t rcs t wp t cwl t wp t wp t dh t ds t ds t dh t ds t off t cpa t cwl t oh t oh t on t dh t on t off t cac t aa t aa t cwd t cpwd t cwd t cac t rac t on t aa t rwd t awd t cwl t ral
18 MB814100D-60/mb814100d-70 description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if cas is held low for the specified setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in prepa- ration for the next cas -before-ras refresh operation. we must be held high for the specified set up time (t wsr ) before ras goes low in order not to enter ?est mode? ras v ih v il a 0 to a 9 cas v ih v il v ih v il we v ih v il d out v oh v ol fig. 11 ?ras ?nly refresh (we = a io = ? or ?? description refresh of dram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1024 row addresses every 16.4-milliseconds. ras -only refresh is performed by keeping cas high throughout the cycle; d pin is kept in a high-impedance state. high-z row address ? or ? high-z ? or ? ras v ih v il d out v oh v ol cas v ih v il fig. 12 ?cas -before?as refresh (address = d in = ??or ?? t rc t ras t rp t rpc t oh t rah t off t crp t asr t ras t rc t rpc t rp t chr t csr t cpn t wsr t whr t off t oh
19 MB814100D-60/mb814100d-70 t wsr description the hidden refresh is executed by keeping cas ??to next cycle, i.e., the output data at previous cycle is kept during next refresh cycle. since the cas is kept low continuously from previous cycle, followed refresh cycle should be cas -before-ras refresh. we must be held ??for the specified set up time (t wsr ) before ras goes ??for the second time in order not to enter ?est mode to be specified later. in addition, when a hidden refresh is executed, cas must be high by the specified timing t crp before read cycle, write cycle, read- write/ read-modify-write or page-mode cycle is executed. ras d in v ih v il a 0 to a 10 cas v ih v il v ih v il v ih v il d out fig. 13 ?hidden refresh cycle ? or ? column row address address valid data out high-z off t valid data i n valid data out high-z valid data i n we v ih v il (read cycle) (read write cycle) [normal mode] [test mode] v ih v il v oh v ol we we v ih v il (read cycle) d out (read write cycle) v ih v il v oh v ol we d in v ih v il t rp t rc t ras t rc t ras t rcd t rad t crp t rah t asc t whr t rrh t ral t cah t cac t rcs t aa t rac t on t cac t rcs t aa t rac t on t off t oh t whr t rwd t awd t cwd t rcs t wp t wsr t dh t ds t wsr t rp t chr t whr t wp t wsr t dh t ds t cwd t awd t rwd t rcs t whr t asr t rsh t off t oh
20 MB814100D-60/mb814100d-70 description test mode ; the purpose of this test mode is to reduce device test time to one eighth of that required to test the device conventionally. the test mode function is entered by performing a we and cas -before-ras (wcbr) refresh for the entry cycle. in the test mode, read and write operations are executed in units of eight bits which are selected by the address combination of ra io , ca o and ca io . in the write mode, data is written into eight cells simultaneously. in the read mode, the data of eight cells at the selected addresses are read back and checked in the following manner. when the eight bits are all ??or all ?? a ??level is output. when the eight bits show a combination of ??and ?? a ??level is output. the test mode function is exited by performing a ras -only refresh or a cas -before-ras refresh for the exit cycle. in test mode operation, the following parameters are delayed approximately 5 ns from the specified value in the data sheet. t rc , t rwc , t rac , t aa , t ras , t csh , t ral , t rwd , t awd , t pc , t prwc , t cpa , t rhcp , t cpwd , t rasp , t rsh , t cas , t cwd , t cac . ras v ih v il cas v ih v il we v ih v il d out v oh v ol fig.14 ?test mode set cycle (a o to a io , d = ??or ?? high-z ? or ? t rc t rp t cpn t csr t chr t rpc t wsr t whr t off t oh t ras t rpc
21 MB814100D-60/mb814100d-70 ras d in v ih v il a 0 to a 10 cas v ih v il v ih v il v ih v il fig. 15 ?cas -before?as refresh counter test cycle valid data out ? or ? valid data high-z column address valid data in description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the func- tionality of cas -before-ras refresh circuitry. if, after a cas -before-ras refresh cycle. cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are defined as follows: row address: bits a 0 through a 9 are defined by the on-chip refresh counter. column address: bits a 0 through a 9 are defined by latching levels on a 0 -a 9 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows ; 1) initialize the internal refresh address counter by using 8 ras only refresh cycles. 2) use the same column address throughout the test. 3) write ??to all 1024 row addresses at the same column address by using normal write cycles. 4) read ??written in procedure 3) and check; simultaneously write ??to the same addresses by using cas - before-ras refresh counter test (read-modify-write cycles). repeat this procedure 1024 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 1024 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). mb814100d-70 MB814100D-60 unit parameter min . max. ns no . min. max. 51 20 15 symbol (at recommended operating conditions unless otherwise noted.) cas to we delay 52 15 ns 15 column address hold 53 cas pulse width 54 ras hold time 20 ns 15 20 ns 15 55 ns 15 35 ns 30 56 cas precharge time 20 access time from cas t fcac t fcah t fcwd t fcas t frsh t cpt assumes that cas -before-ras refresh counter test cycle only. we v ih v il (read cycle) d out v oh v ol we v ih v il (read cycle) t chr t csr t cpr t frsh t fcas t rp t ral t fcah t asc t wsr t whr t rcs t fcac t on t rcs t fcwd t ds t cwl t rwl t wp t dh t rrh t oh t rch t off
22 MB814100D-60/mb814100d-70 n package dimensions c 1995 fujitsu limited c26054s-3c-1 lead no "a" 15.24(.600)ref 17.150.13(.675.005) 1.27(.050)typ 2.54(.100)typ 7.62 nom (.300) 8.430.13 (.332.005) index 1 5 9 13 14 18 22 26 2.25(.089)nom 0.64(.025)min r0.81(.032)typ 6.810.51 (.268.020) 0.81(.032)max 0.430.10(.017.004) details of "a" part 2.50(.098)nom 0.10(.004) * 3.40 +0.35 ?0.20 +.014 ?.008 .134 .008 ?.001 +.002 ?0.02 +0.05 0.20 26 pin, plastic soj (lcc-26p-m04) dimensions in mm(inches).
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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